BMA280 configuration failure after soft reset

[ajcurtis84]

Hello,

I have implemented a write/verify chip configuration routine. If the configuration process is preceeded with a "Soft Reset w/2ms delay", verification of register FIFO_CONFIG_1 (0x3E) fails. It always returns 0x00. If I don't perform the soft reset, the configuration verification works fine.

Has anyone else experienced this? Is there a solution?

Thanks

[Minhwan]

Hello, 

Could you share your source code? 

Thank you.

[MarkPMendelsohn]

66 // Initialize
67 static uint8_t NRF_TWI_MNGR_BUFFER_LOC_IND bma280_softreset_config[] =
68 {
69 BMA280_BGW_SOFTRESET, 0xB6 ///< Soft Reset
70 };
71
72 static uint8_t NRF_TWI_MNGR_BUFFER_LOC_IND bma280_config[] =
73 {
74 BMA280_PMU_LPW, 0x50, ///< low power mode enabled and 4ms sleep time (to fulfill the 1/(2*bw)=n*sle ep requirement)
75 BMA280_PMU_LOW_NOISE, 0x60, ///< low power mode 2 and EST sampling on
76 BMA280_PMU_RANGE, 0x03, ///< 2g accelerometer g-range
77 BMA280_PMU_BW, 0x09, ///< 15.63 Hz BW
78 BMA280_INT_MAP_0, 0x10, ///< Map double tap interrupt to INT1
79 BMA280_INT_MAP_1, 0x20, ///< Map FIFO full to INT2
80 BMA280_INT_OUT_CTRL, 0x05, ///< Pins at high when interrupt active
81 BMA280_INT_8, 0x05, ///< TBD standard settings but extending the double tap window to 375ms
82 BMA280_INT_9, 0x81, ///< Use 8 samples in low power mode, threshold at (62.5 mg (62.5mg * bits wi th current settings)
83 BMA280_FIFO_CONFIG_1, 0x80, ///< Stream mode (discards data is too slow) for all 3 axes for the FIFO
84 };

196 static bool init_bma280(void)
197 {
198 uint8_t *soft_reset = bma280_softreset_config;
199
200 nrf_twi_mngr_transfer_t xfer = NRF_TWI_MNGR_WRITE(BMA280_ADDRESS, soft_reset, 2, 0);
201 APP_ERROR_CHECK( nrf_twi_mngr_perform(&m_nrf_twi_mngr, NULL, &xfer, 1, NULL) );
202 nrf_delay_us(2000);
203
204 // Set each register indivually, with the necessary delay
205 uint8_t *reg_val = bma280_config;
206
207 for (unsigned i = 0; i < sizeof(bma280_config)/2; i++)
208 {
209 nrf_twi_mngr_transfer_t xfer = NRF_TWI_MNGR_WRITE(BMA280_ADDRESS, reg_val, 2, 0);
210 APP_ERROR_CHECK( nrf_twi_mngr_perform(&m_nrf_twi_mngr, NULL, &xfer, 1, NULL) );
211 nrf_delay_us(2);
212
213 reg_val += 2;
214 }
215
216 // Read back and verify
217 reg_val = bma280_config;
218 for (unsigned i = 0; i < sizeof(bma280_config)/2; i++)
219 {
220 uint8_t value = 0;
221 nrf_twi_mngr_transfer_t read_xfer[] =
222 {
223 NRF_TWI_MNGR_WRITE(BMA280_ADDRESS, &reg_val[0], sizeof(uint8_t), NRF_TWI_MNGR_NO_STOP),
224 NRF_TWI_MNGR_READ(BMA280_ADDRESS, &value, sizeof(value), 0)
225 };
226
227 APP_ERROR_CHECK( nrf_twi_mngr_perform(&m_nrf_twi_mngr, NULL, read_xfer, 2, NULL) );
228
229 if (value != reg_val[1])
230 {
231 #if TRACE_TWI_SENSORS || TRACE_STARTUP
232 NRF_LOG_INFO("BMA280 reg 0x%02x mismatch 0x%0x != 0x%02x", reg_val[0], value, reg_val[1]);
233 #endif

234

235 return false;
236 }
237
238 reg_val += 2;
239 }

[MarkPMendelsohn]

If the Soft Reset is performed before the rest of the configuration, the read-after-write of register 0x3E will result in a mismatch. Reading 0x00 instead of 0x80. If the Soft Reset is not performed, the read-after-write of the 0x3E register will match.

[MarkPMendelsohn]

00> [00:00:00.010,253] <info> accel: BMA280 Soft Reset Performed
00> [00:00:00.014,892] <info> accel: BMA280 reg 0x11 match 0x50 == 0x50
00> [00:00:00.015,441] <info> accel: BMA280 reg 0x12 match 0x60 == 0x60
00> [00:00:00.015,991] <info> accel: BMA280 reg 0x0F match 0x3 == 0x03
00> [00:00:00.016,510] <info> accel: BMA280 reg 0x10 match 0x9 == 0x09
00> [00:00:00.018,096] <info> accel: BMA280 reg 0x19 match 0x10 == 0x10
00> [00:00:00.018,646] <info> accel: BMA280 reg 0x1A match 0x20 == 0x20
00> [00:00:00.019,195] <info> accel: BMA280 reg 0x20 match 0x5 == 0x05
00> [00:00:00.019,714] <info> accel: BMA280 reg 0x2A match 0x5 == 0x05
00> [00:00:00.022,308] <info> accel: BMA280 reg 0x2B match 0x81 == 0x81
00> [00:00:00.022,857] <info> accel: BMA280 reg 0x3E mismatch 0x0 != 0x80