BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

[BSTRobin]

Hi jwhistle,

You could refer previous attached BMA456 example code.

[david_cy_kao]

Hi all,
  We set the BMA456 as non-latch mode, odr = 50Hz and watermark = 300. Measure the  waveform of the interrupt pin, we can see there is one sudden pull low and pull high signal (interval = 165ns). This signal causes mcu receives 2 IRQ  every 1 second.
= log (read int_status) =
GPIO high
int_status: 0200
FIFO data bytes available: 300
Parsed accelerometer data frames: accel_length = 50
end-int_status: 0000
GPIO low
int_status: 0000
FIFO data bytes available: 18
Parsed accelerometer data frames: accel_length = 3
end-int_status: 0000


Per the test, if we don't read the int_status when IRQ occurs, the waveform would not see this pull low and pull high signal. The mcu only receives 1 IRQ every 1 second. 
= log (skip read int_status) =
GPIO high
FIFO data bytes available: 300
Parsed accelerometer data frames: accel_length = 50
GPIO high
FIFO data bytes available: 300
Parsed accelerometer data frames: accel_length = 50
GPIO high
FIFO data bytes available: 300
Parsed accelerometer data frames: accel_length = 50

void bma_read_irq(void) {
   ...
   rslt = bma456_an_read_int_status(&int_status, &dev);  ----> If not read int_status, the waveform would not see this sudden pull low and pull high signal
   if(rslt == BMA4_OK) {
      bma4_get_fifo_length(&fifo_length, &bma456_dev);
      ...
      bma4_read_fifo_data(&fifoframe, &bma456_dev);
      ...
   }
}

Please help to check my test result and kindly share your suggestion if you ever encounter the same problem. Thanks.

[BSTRobin]

Hi david_cy_kao,

After reading interrupt status register, status register and interrupt line will be cleared, but condition still hold when it is cleared, interrupt will assert again.

You could map one interrupt pin to FIFO watermark interrupt, such as INT2 was only used for it. When host MCU receive interrupt from INT2, don't read interrupt status register, then it will not have two interrupts.

[david_cy_kao]

Hi BSTRobin,
  Thanks for the clarification for this symptom. Even we use the latched mode, we still can see this 2nd interrupt. It seems this the chip design limitation. Currently we use a workaround to avoid the 2nd interrupt. Per the previous log, the int_status of the 2nd interrupt would be 0. If we read the int_status is 0, we do nothing. (This is the same way as the code in your example code: fifo_watermark_headerless_mode)
 
//Read INT_STATUS
rslt = bma456_an_read_int_status(&int_status, &bma456_dev);
if (rslt == BMA4_OK) {
//printf("int_status: %04x\n\r", int_status);
if (int_status == 0) {
 return;
}

[BSTRobin]

Hi david_cy_kao,

It is better to use non-latched(default mode) mode for your application.
You can refer previous reference I uploaded which only triggle one interrupt when host run fifo_watermark example.