Most SPI devices auto-increment the address if multiple bytes are read or written as long as the chip select is kept active. We're seeing weird behavior with register writes, and the spec sheet is vague on this question.
When discussing 3-wire SPI, page 89 of the spec sheet says: "For single byte read as well as write operation, 16-bit protocols are used." Not exactly sure what "16-bit protocols" are in the context of SPI. Then it goes on to say: "The BMI160 also supports multiple-byte read and write operations." That sounds encouraging, other than the question of what "16-bit protocols" means in the preceding sentence.
But later, on page 91, the spec sheet says: "Multiple read operations are possible by keeping CSB low and continuing the data transfer. Only the first register address has to be written. Addresses are automatically incremented after each read access as long as CSB stays active low." [emphasis mine] Immediately afterward is Figure 25, which illustrates "the principle of multiple read" and shows a single address byte followed by multiple, auto-incremented read bytes of data.
Importantly, there is no explicit mention of "multiple read operations by keeping CSB low" and there is no similar illustration like Figure 25 for "SPI multiple write". Yet page 89 clearly states "The BMI160 also supports multiple-byte read and write operations."
Which is correct? Page 89 that says multibyte writes should work, or page 91 which describes multibyte reads but is utterly silent about multibyte writes? And what does "16-bit protocol" mean in SPI mode when every example in the spec sheet shows 8-bit addresses and 8-bit data being exchanged?
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