BMI160 Latched/non-latched/temporary interrupt modes really missing for BMI270?

[BuzzyBuzz]

BMI160 has the register 0x54 INT_LATCH <3:0> where you can filter interrupts. 

For instance, if having a lot of interrupts, you may set this register to only allow pin interrupt for instance as often as every 640ms (preventing spamming the cpu).

Is this feature gone for BMI270? Do I really have to filter this in CPU?

[BSTRobin · Accepted solution]

Hi BuzzyBuzz,

BMI270 didn't have temporary setting, when receiving an interrupt, read the interrupt status register to determine which interrupt has occurred.