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    bma456 - headerless watermark mode

    TMunb
    New Poster

    bma456 - headerless watermark mode


    hi Bosch,

    I have a BMA456 accelerometer connected to an STM32 micro via I2C.

    Based on your BMA456-Sensor-API examples I see the following:

    accelerometer.c:
    in this example are included both sensor initialisation and writing of the config file ...

    /* Sensor initialization */
    rslt = bma456_init(&bma);
    /* Upload the configuration file to enable the features of the sensor. */
    rslt = bma456_write_config_file(&bma);

    Further below int1 is mapped, and when the interrupt status indicates data is ready the data is read ...

    /* Mapping data ready interrupt with interrupt pin 1 to get interrupt status once getting new accel data */
    rslt = bma456_map_interrupt(BMA4_INTR1_MAP, BMA4_DATA_RDY_INT, BMA4_ENABLE, &bma);

    while (1)
    {
    /* Read interrupt status */
    rslt = bma456_read_int_status(&int_status, &bma);
    /* Filtering only the accel data ready interrupt */
    if ((rslt == BMA4_OK) && (int_status & BMA4_ACCEL_DATA_RDY_INT))
    {
    /* Read the accel x, y, z data */
    rslt = bma4_read_accel_xyz(&sens_data, &bma);

    Is there a specification in the datasheet or elsewhere indicating how much time will be taken for the interrupt to indicate that data is ready ? Is it basically governed only by the odr setting, in this case 50Hz, and the number of samples so 1/50 x 3 = 60ms ?

    The above code seems to work well in our application (once I change BMA4_I2C_ADDR_PRIMARY UINT8_C(0x18) to BMA4_I2C_ADDR_PRIMARY UINT8_C(0x18<<1) ) although it's actually headerless watermark mode which is more applicable for our product.

    fifo_watermark_headerless_mode.c:
    now using this example we note sensor initialisation is still used, but not the writing of the config file ...

    /* Initialize BMA456 */
    rslt = bma456_init(&dev);

    Why is writing of the config file not used in this example ? Should I manually add this so that it appears as in accelerometer.c ? I've tried this example with and without writing of the config file, and it doesn't seem to make a difference hence would like to know which is correct and why, please ?

    As with the first example is there a way to calculate in this headerless watermark mode example how much time is needed for the device to prepare the samples and indicate completiong via int1 ? Now with odr = 100Hz would it be 1/100 x 100 samples = 1 second ?

    And at what point in this code example does the BMA456 begin the process of collecting the samples (100 samples, so 100x6 = 600 which is the watermark level set in the code) ? Or is the device continually recording samples and storing these in its FIFO, but just asserting int1 once 600 has been reached after which it continues to collect and record more samples ?

    I'm not properly understanding the watermark mode of operation, so can you help me to understand a little better, please ? I know the FIFO is 1024 bytes in total, and in this example watermark is set to 600 (which in headerless mode equates to 100 samples of x, y, and z because 600 / 6 = 100, and each sample group of x, y, and z is 3 x 2 bytes). Assuming the device begins filling its internal memory at "address 0" and continues until "address 1023" then is it true to say it will assert the mapped interrupt, in this case int1, when it reaches "address 599" ? Does it then continue filling memory upto "address 1023" but then assert int1 again (assuming it remains in the same mode) when it again reaches "address 599" ? Or does this all depend on the FIFO overflow setting ? So if I choose BMA4_FIFO_STOP_ON_FULL then will it stop sampling and filling the FIFO once it reaches "address 1023" ? And if this setting is not chosen will it continually sample and record going back to the start of FIFO after reaching the full mark ?

    The bandwidth setting in the example is BMA4_ACCEL_NORMAL_AVG4 so does that mean each sample finally read, after int1 is asserted, is actually the average of 4 samples ? How does this setting affect my calculated duration, above, of 1 second ? This is I believe with acc_perf_mode choosing cic_avg/averaging mode. If instead I set acc_perf_mode to continous filter function mode does this mean each and every sample is just the first raw value meaning without any averaging applied ? And then is this identical to remaining in averaging mode, but with an acc_bwp setting of BMA4_ACCEL_OSR4_AVG1 ?

    This code example includes the following comment:

    /* Disabling advance power save mode as FIFO data is not accessible in advance low power mode */
    rslt = bma4_set_advance_power_save(BMA4_DISABLE, &dev);

    The datasheet describes bit fifo_self_wakeup and states that with this bit set "FIFO read enabled after interrupt in advanced power saving mode". Does this mean that in your example advanced power save mode could've been employed throughout the time the device was sampling and recording these accelerometer values to its FIFO, but that we would then need to exit this low power mode to actually read the values from FIFO ? The datasheet actually states "The sensors log data into the FIFO in performance and low power mode (by low power mode do they also mean advanced power save mode ?) . When the FIFO watermark interrupt is active (it is in this example), the FIFO is accessible for reading in low power mode until a burst read operation on Register FIFO_DATA completes when PWR_CONF.fifo_self_wakeup=0b1". Once int1 has been asserted I believe this example does complete such a burst read on FIFO_DATA, using bma4_read_fifo_data(), so does this mean the entire process can be performed in advanced power saving mode ?

    6 REPLIES 6
    BSTRobin
    Community Moderator

    Re: bma456 - headerless watermark mode

    Hello TMunb,

    The configuration file contains the algorithm implementation of the feature(like step counter, activity, etc.). If you need to use the feature, you need to load the configuration file. If you read only sensor data, you don't need to load the configuration file.

    If you configured ODR to 50 Hz, data ready will occur every 20 ms.

    BMA4_ ACCEL_ NORMAL_ Avg4 is an internal sampling parameter. The time you read data is determined by ODR.

    When you enable fifo_self_wakeup and used FIFo watermark interrupt under low power mode, after the interrupt is triggered, the sensor will automatically switch from low power mode to normal mode.

    TMunb
    New Poster

    Re: bma456 - headerless watermark mode


    hi BSTRobin,

    having read the bma456 datasheet it's not clear, to me, what features do require writing of the configuration file and which do not, sorry. Is this documented anywhere ? Is there another relevant Bosch reference document apart from this bma456 datasheet ? Can I at least assume that the config file is not required for implementation of any part of FIFO/watermark mode ? What specific part of example accelerometer.c requires the config file to be written ?

    With ODR = 50Hz then data is ready at 3 x 20ms (3 channels, x, y and z) = 60ms regardless of bandwidth setting and g-range - is that correct ?

    By "low power mode" do they also mean "advanced power save mode" - are these two modes the same thing ?

    "When you enable fifo_self_wakeup and used FIFo watermark interrupt under low power mode, after the interrupt is triggered, the sensor will automatically switch from low power mode to normal mode." Based on this answer does it mean that we do not need to disable advance power save mode, as is done in the example which uses rslt = bma4_set_advance_power_save(BMA4_DISABLE, &dev), but can instead enable fifo_self_wakeup such that the sensors can still log data into the FIFO while in low power/advanced power save mode until the interrupt is triggered at which point the device automatically enters normal mode ready for FIFO data to be accessed via I2C ? If so then in this case can we expect current consumption to drop from 150uA which is typical for performance mode down to 14uA which is typical for low power mode ? If the sensors log data into the FIFO in performance and low power mode then what if any penalty is paid by doing this in low power mode as opposed to performance mode apart from not having the same available range of odr ? Just wondering why you would intentionally do this in performance mode if the results are identical in low power mode where current consumption is less.

    The fifo_watermark_headerless_mode.c example I've been referring to disables advanced power mode and uses the bandwidth setting of BMA4_ACCEL_NORMAL_AVG4. Page 58/102 of the bma456 datasheet defines the bandwidth parameter and for acc_bwp of 0x02, which corresponds to BMA4_ACCEL_NORMAL_AVG4, states "acc_perf_mode = 1 -> normal mode; acc_perf_mode = 0 -> average 4". So does that mean the example applied no averaging as it was in performance mode, but if I change to low power mode still with BMA4_ACCEL_NORMAL_AVG4 it will apply an average for each of x, y, and z based on 4 samples for each ? The same table on page 58 mentions OSR2 and OSR4 mode - what are they ?

    Can you please help me to properly understand FIFO/watermark operation by responding to my middle paragraph in my previous post which is copy and pasted below ?

    "I'm not properly understanding the watermark mode of operation, so can you help me to understand a little better, please ? I know the FIFO is 1024 bytes in total, and in this example watermark is set to 600 (which in headerless mode equates to 100 samples of x, y, and z because 600 / 6 = 100, and each sample group of x, y, and z is 3 x 2 bytes). Assuming the device begins filling its internal memory at "address 0" and continues until "address 1023" then is it true to say it will assert the mapped interrupt, in this case int1, when it reaches "address 599" ? Does it then continue filling memory upto "address 1023" but then assert int1 again (assuming it remains in the same mode) when it again reaches "address 599" ? Or does this all depend on the FIFO overflow setting ? So if I choose BMA4_FIFO_STOP_ON_FULL then will it stop sampling and filling the FIFO once it reaches "address 1023" ? And if this setting is not chosen will it continually sample and record going back to the start of FIFO after reaching the full mark ?"

    Thank-you in advance.

    TMunb
    New Poster

    Re: bma456 - headerless watermark mode


    hi BSTRobin,

    please do respond here, thank-you.

     

    BSTRobin
    Community Moderator

    Re: bma456 - headerless watermark mode

    Hello TMunb,

    having read the bma456 datasheet it's not clear, to me, what features do require writing of the configuration file and which do not, sorry. Is this documented anywhere ? Is there another relevant Bosch reference document apart from this bma456 datasheet ? Can I at least assume that the config file is not required for implementation of any part of FIFO/watermark mode ? What specific part of example accelerometer.c requires the config file to be written ?

    Reply:There features needed config file support. It is recommended that you load the configuration file by default.

    BMA456 supported feature.png

    With ODR = 50Hz then data is ready at 3 x 20ms (3 channels, x, y and z) = 60ms regardless of bandwidth setting and g-range - is that correct ?

    reply: data ready time is 20 ms if you set ODR to 50 Hz.

    By "low power mode" do they also mean "advanced power save mode" - are these two modes the same thing ?

    Reply: you could see power mode from data sheet like this:

    BMA456 power mode.png

    "When you enable fifo_self_wakeup and used FIFo watermark interrupt under low power mode, after the interrupt is triggered, the sensor will automatically switch from low power mode to normal mode." Based on this answer does it mean that we do not need to disable advance power save mode, as is done in the example which uses rslt = bma4_set_advance_power_save(BMA4_DISABLE, &dev), but can instead enable fifo_self_wakeup such that the sensors can still log data into the FIFO while in low power/advanced power save mode until the interrupt is triggered at which point the device automatically enters normal mode ready for FIFO data to be accessed via I2C ? If so then in this case can we expect current consumption to drop from 150uA which is typical for performance mode down to 14uA which is typical for low power mode ? If the sensors log data into the FIFO in performance and low power mode then what if any penalty is paid by doing this in low power mode as opposed to performance mode apart from not having the same available range of odr ? Just wondering why you would intentionally do this in performance mode if the results are identical in low power mode where current consumption is less.

    Reply: yes, don't need to swith power mode to normal mode mannualy. FIFO data is always stored in low-power mode. When it is necessary to read data, switch to normal mode. The time for reading data is very short, which has little impact on power consumption.

    The fifo_watermark_headerless_mode.c example I've been referring to disables advanced power mode and uses the bandwidth setting of BMA4_ACCEL_NORMAL_AVG4. Page 58/102 of the bma456 datasheet defines the bandwidth parameter and for acc_bwp of 0x02, which corresponds to BMA4_ACCEL_NORMAL_AVG4, states "acc_perf_mode = 1 -> normal mode; acc_perf_mode = 0 -> average 4". So does that mean the example applied no averaging as it was in performance mode, but if I change to low power mode still with BMA4_ACCEL_NORMAL_AVG4 it will apply an average for each of x, y, and z based on 4 samples for each ? The same table on page 58 mentions OSR2 and OSR4 mode - what are they ?

    Reply:acc_bwp had different meaning acooding acc_perf_mode value. If acc_perf_mode was set to 0, the sampling will be averaged. You could see it from data sheet.

    BMA456 acc_bwp.png

    Can you please help me to properly understand FIFO/watermark operation by responding to my middle paragraph in my previous post which is copy and pasted below ?

    "I'm not properly understanding the watermark mode of operation, so can you help me to understand a little better, please ? I know the FIFO is 1024 bytes in total, and in this example watermark is set to 600 (which in headerless mode equates to 100 samples of x, y, and z because 600 / 6 = 100, and each sample group of x, y, and z is 3 x 2 bytes). Assuming the device begins filling its internal memory at "address 0" and continues until "address 1023" then is it true to say it will assert the mapped interrupt, in this case int1, when it reaches "address 599" ? Does it then continue filling memory upto "address 1023" but then assert int1 again (assuming it remains in the same mode) when it again reaches "address 599" ? Or does this all depend on the FIFO overflow setting ? So if I choose BMA4_FIFO_STOP_ON_FULL then will it stop sampling and filling the FIFO once it reaches "address 1023" ? And if this setting is not chosen will it continually sample and record going back to the start of FIFO after reaching the full mark ?"

    Reply:When the FIFO length reaches 600 bytes, an interrupt will be triggered. At this time, the host needs to read the FIFO, otherwise the FIFO length will continue to increase. If the host reads 600 bytes of FIFO data, the FIFO length starts from 0 and then increases. If you choose BMA4_FIFO_STOP_ON_FULL. When FIFO was full, it willn't store latest new data to FIFO.

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