In my design, set acce and gyro odr in 400hz and set sync according to the BMI08x-Sensor-API-master from github.The CPU reads acce and gyro FIFO once every 0.1s. But the fifo length is not equal between acce and gyro. Sometimes the acce are 41 frames and gyro are 39 frames(in normal should output 40 frames).
The question one is Why do accelerometers output one more frame of data?
The question two is how to sync acce and gyro in fifo mode?
Yes, it should be 40 frame number according your parameter setting.
When MCU read ACC & GYRO data once every 0.1S, to get 40 frame FIFO data the 0.1S interval must be accurate.
Could you check 0.1S interval time?
I'm using fifo warm mark interrupt to read data instead of timer.When I set 280 bytes to trigger interrupt,the acce I can get 40 frames but gyro sometimes just have 39 frames.
According to bmi088_master project of git hub, I set synce between acce and gyro.There are registers I can't found descript in datasheet.for example :
static const uint8_t ACC_INIT_CTRL_ADDR = 0x59;
static const uint8_t ACC_FEATURE_LSB_ADDR = 0x5B;
static const uint8_t ACC_FEATURE_MSB_ADDR = 0x5C;
static const uint8_t ACC_FEATURE_CFG_ADDR = 0x5E;
1、Are these private regsiger ?
2、How I achieve acce and gyro sync?
You will see 0x59~0x6B registers were reserved in data sheet.
If you set 400 Hz ODR and read data every 0.1 s. For high ODR application scenario, most application read RAW data with high spped(ms). Can your application accept reading data every 0.1 second? It is better to directly read RAW data if you set ODR with a high value.
By the way, which communication interface(SPI or I2C) you use?