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    usage of BMa425 FIFO

    Neverweak
    New Poster

    usage of BMa425 FIFO

    I'm trying to understand how to configure the BMA425 so that I can read the FIFO when a FIFO_WaterMark interrupt occurs.  Here is how I have the BMA425 configured at the moment.After this configration,all data of axsi is read out,but no interrupt signal triggers (no low level output from  pin int1 )

    Am i need to do anything esle ? txs much!

    bma4_write_regs(BMA4_INIT_CTRL_ADDR, &config_load, 1, &BMA425_DEV); //INIT_CRL 0
    bma423_set_remap_axes(&BMA425_AXES_Config,&BMA425_DEV);
    bma423_anymotion_enable_axis(BMA423_ALL_AXIS_EN,&BMA425_DEV);
    bma4_write_regs(BMA4_INIT_CTRL_ADDR, &config_load, 1, &BMA425_DEV); //INIT_CRL 1
    BMA425_DEV.delay(150);
    bma4_set_accel_config(&BMA425_Accel_Config,&BMA425_DEV);
    bma4_set_accel_enable(BMA4_ENABLE,&BMA425_DEV);
    bma423_map_interrupt(BMA4_INTR1_MAP,BMA4_FIFO_FULL_INT,BMA4_ENABLE,&BMA425_DEV);
    bma4_set_fifo_config(BMA4_FIFO_ACCEL,BMA4_ENABLE,&BMA425_DEV);
    bma4_set_fifo_wm(600,&BMA425_DEV);
    bma4_set_int_pin_config(&BMA425_PIN_Config,BMA4_INTR1_MAP,&BMA425_DEV);

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    1 REPLY 1
    DavidDai
    Member

    Re: usage of BMa425 FIFO

    Dear user,

    it depends on how you configure the int pin electrical behavior, by default the INT1&INT2 pins are disabled, so you need to properly enable the output and active level, and the push-pull/open drain behavior.

    normally, once:

    1. the acc_en in reg0x7D is enabled,

    2. fifo_acc_en is enabled in reg0x48,

    3. fwm/ffull is mappeded in reg0x58,

    4. configure INT1/INT2 pin output in reg0x53&0x54

    the corresponding interrupt will be enabled, you should see the interrupt signaled out.

    if this issue still there, you'd better dump all the register map and share to us. better to check the waveform of initialization and interrupt behavior(spi/i2c + INT1) with logic analysor.

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