Hello Just to check a couple of things to better help you. 1) what is the ODR used for the issue concerned? 2) are you using i2c/spi to talk to the sensor? 3) did you enable fifo_time_en in FIFO_CONFIG0 (register 0x26), when reading FIFO, it's suggested to enable fifo_time_en bit so that you get the sensortime frame which is an indication the sensor fifo is completely read out The FIFO is automatically filled even during the time when you are reading out the samples from it, so it could be possible that: if the reading out is on the verge of a new sample arrival, after the read out, the FIFO is not drained compeletely, this is usually the case when: the system is very busy, and read out of the FIFO is delayed long after latest sample is available, or if the ODR is high and a very slow bus is used(e.g.: 100khz I2C), so to address this kind of tricky timing issue (from the host), the driver tries to overread a bit. `` if ((fifo->fifo_time_enable == BMA400_ENABLE) && (fifo_byte_cnt + BMA400_FIFO_BYTES_OVERREAD <= user_fifo_len)) { /* Handling sensor time availability*/ fifo->length = fifo->length + BMA400_FIFO_BYTES_OVERREAD; } `` BMA400_FIFO_BYTES_OVERREAD is currently defined as 25, please note that it's a number with tradeoff between traffic size and changes of improving the issue, if this number is very big, then you can almost guarrantee that everytime you can drain the fifo completely, but the overhead on the bus traffic is higher, vice versa. and the number 25 has already covered the dummy byte. but this overread only is applied when the fifo_time_en bit is set. Hope this helps.
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