About david_cy_kao

david_cy_kao · ‎03-27-2023

Hi BSTRobin, Thanks for the clarification for this symptom. Even we use the latched mode, we still can see this 2nd interrupt. It seems this the chip design limitation. Currently we use a workaround to avoid the 2nd interrupt. Per the previous log, the int_status of the 2nd interrupt would be 0. If we read the int_status is 0, we do nothing. (This is the same way as the code in your example code: fifo_watermark_headerless_mode) //Read INT_STATUS rslt = bma456_an_read_int_status(&int_status, &bma456_dev); if (rslt == BMA4_OK) { //printf("int_status: %04x\n\r", int_status); if (int_status == 0) { return; }

david_cy_kao · ‎03-24-2023

Hi all, We set the BMA456 as non-latch mode, odr = 50Hz and watermark = 300. Measure the waveform of the interrupt pin, we can see there is one sudden pull low and pull high signal (interval = 165ns). This signal causes mcu receives 2 IRQ every 1 second. = log (read int_status) = GPIO high int_status: 0200 FIFO data bytes available: 300 Parsed accelerometer data frames: accel_length = 50 end-int_status: 0000 GPIO low int_status: 0000 FIFO data bytes available: 18 Parsed accelerometer data frames: accel_length = 3 end-int_status: 0000 Per the test, if we don't read the int_status when IRQ occurs, the waveform would not see this pull low and pull high signal. The mcu only receives 1 IRQ every 1 second. = log (skip read int_status) = GPIO high FIFO data bytes available: 300 Parsed accelerometer data frames: accel_length = 50 GPIO high FIFO data bytes available: 300 Parsed accelerometer data frames: accel_length = 50 GPIO high FIFO data bytes available: 300 Parsed accelerometer data frames: accel_length = 50 void bma_read_irq(void) { ... rslt = bma456_an_read_int_status(&int_status, &dev); ----> If not read int_status, the waveform would not see this sudden pull low and pull high signal if(rslt == BMA4_OK) { bma4_get_fifo_length(&fifo_length, &bma456_dev); ... bma4_read_fifo_data(&fifoframe, &bma456_dev); ... } } Please help to check my test result and kindly share your suggestion if you ever encounter the same problem. Thanks.

david_cy_kao · ‎03-10-2023

Thanks for the example code and the information. After checking the code, the configuration and flow are the same but I still see these irq. It may be the HW issue and I now test with HW guys. Once we have any furthur anslysis, I will update the information.

david_cy_kao · ‎03-06-2023

Refer sample code (bma456an_examples/fifo_watermark_headerless_mode/) BMA456-Sensor-API/fifo_watermark_headerless_mode.c at master · boschsensortec/BMA456-Sensor-API · GitHub I use the below setting to enable the BMA456 fifo interrupt: // Set Accel Config (0x40) bma456_cfg.bandwidth = BMA4_ACCEL_NORMAL_AVG4; bma456_cfg.odr = BMA4_OUTPUT_DATA_RATE_50HZ; bma456_cfg.perf_mode = BMA4_CONTINUOUS_MODE; bma456_cfg.range = BMA4_ACCEL_RANGE_2G; rslt = bma4_set_accel_config(&bma456_cfg, &bma456_dev); // Enable the accelerometer rslt = bma4_set_accel_enable(BMA4_ENABLE, &bma456_dev); //Clear FIFO configuration register rslt = bma4_set_fifo_config(BMA4_FIFO_HEADER ,BMA4_DISABLE, &bma456_dev); // Configure Interrupts struct bma4_int_pin_config int_pin_config; int_pin_config.edge_ctrl = BMA4_LEVEL_TRIGGER; int_pin_config.input_en = BMA4_INPUT_DISABLE; int_pin_config.lvl = BMA4_ACTIVE_HIGH; int_pin_config.od = BMA4_PUSH_PULL; int_pin_config.output_en = BMA4_OUTPUT_ENABLE; bma4_set_int_pin_config(&int_pin_config, BMA4_INTR1_MAP, &bma456_dev); // Map INT1 Interrupt to FIFO_WM_INT rslt = bma4_map_interrupt(BMA4_INTR1_MAP, BMA4_FIFO_WM_INT, BMA4_ENABLE, &bma456_dev); //SET watermark rslt = bma4_set_fifo_wm(BMA_FIFO_WATERMARK, &bma456_dev); // Enable the accelerometer FIFO rslt = bma4_set_fifo_config(BMA4_FIFO_ACCEL, BMA4_ENABLE, &bma456_dev); When my device receives interrupt, it will read the int_status and the fifo buffer frame. I suppose the interrupt is received 50 samples (300 bytes) every 1 second (due to the ODR is set to 50Hz). But the log shows the device receives 2 interrupts: - 1st interrupt: status is 0200 (fwm_int) - 2nd interrupt: statis is 0000 I also check interrupt regster: 0x53: 0A 0x54: 00 0x58: 02 == log == [06/03/23 - 17:19:54:819] BMA__IRQ [06/03/23 - 17:19:54:822] int_status: 0200 [06/03/23 - 17:19:54:839] FIFO data bytes available : 300 [06/03/23 - 17:19:54:872] Parsed accelerometer data frames: length = 50 [06/03/23 - 17:19:54:886] BMA__IRQ [06/03/23 - 17:19:54:886] int_status: 0000 [06/03/23 - 17:19:54:894] FIFO data bytes available : 24 [06/03/23 - 17:19:54:919] Parsed accelerometer data frames: length = 4 [06/03/23 - 17:19:55:880] BMA__IRQ [06/03/23 - 17:19:55:886] int_status: 0200 [06/03/23 - 17:19:55:899] FIFO data bytes available : 300 [06/03/23 - 17:19:55:936] Parsed accelerometer data frames: length = 50 [06/03/23 - 17:19:55:949] BMA__IRQ [06/03/23 - 17:19:55:949] int_status: 0000 [06/03/23 - 17:19:55:956] FIFO data bytes available : 24 [06/03/23 - 17:19:55:980] Parsed accelerometer data frames: length = 4 May you kindly help to check the code flow and the log, provide us the possible reason why there is another interrupt (0000)? Is there any method to avoid it? Thanks

Bosch Shared

About david_cy_kao

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

About david_cy_kao

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

Re: BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

BMA456 sends multiple fifo interrupt (BMA4_FIFO_WM_INT)

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