Thanks, But We have only INT1 pin connected to MCU, INT2 is not connected to mcu. Any other method to detect free fall?
Reply: we haven't tested it like this. It depends on whether the host can handle it in time. You can test it on your device.
I want, when device fall on surface that time sensor only generate Free fall interrupt, do not generate tilt interupt that time. Is it possible on INT1 pin?
Any method to diffrentiate free fall and tilt on INT1 pin?
Reply: normally, free fall and tilt willn't occur the interrupt at the same time. You could map them to one interrupt pin.
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having read the bma456 datasheet it's not clear, to me, what features do require writing of the configuration file and which do not, sorry. Is this documented anywhere ? Is there another relevant Bosch reference document apart from this bma456 datasheet ? Can I at least assume that the config file is not required for implementation of any part of FIFO/watermark mode ? What specific part of example accelerometer.c requires the config file to be written ?
Reply:There features needed config file support. It is recommended that you load the configuration file by default.
With ODR = 50Hz then data is ready at 3 x 20ms (3 channels, x, y and z) = 60ms regardless of bandwidth setting and g-range - is that correct ?
reply: data ready time is 20 ms if you set ODR to 50 Hz.
By "low power mode" do they also mean "advanced power save mode" - are these two modes the same thing ?
Reply: you could see power mode from data sheet like this:
"When you enable fifo_self_wakeup and used FIFo watermark interrupt under low power mode, after the interrupt is triggered, the sensor will automatically switch from low power mode to normal mode." Based on this answer does it mean that we do not need to disable advance power save mode, as is done in the example which uses rslt = bma4_set_advance_power_save(BMA4_DISABLE, &dev), but can instead enable fifo_self_wakeup such that the sensors can still log data into the FIFO while in low power/advanced power save mode until the interrupt is triggered at which point the device automatically enters normal mode ready for FIFO data to be accessed via I2C ? If so then in this case can we expect current consumption to drop from 150uA which is typical for performance mode down to 14uA which is typical for low power mode ? If the sensors log data into the FIFO in performance and low power mode then what if any penalty is paid by doing this in low power mode as opposed to performance mode apart from not having the same available range of odr ? Just wondering why you would intentionally do this in performance mode if the results are identical in low power mode where current consumption is less.
Reply: yes, don't need to swith power mode to normal mode mannualy. FIFO data is always stored in low-power mode. When it is necessary to read data, switch to normal mode. The time for reading data is very short, which has little impact on power consumption.
The fifo_watermark_headerless_mode.c example I've been referring to disables advanced power mode and uses the bandwidth setting of BMA4_ACCEL_NORMAL_AVG4. Page 58/102 of the bma456 datasheet defines the bandwidth parameter and for acc_bwp of 0x02, which corresponds to BMA4_ACCEL_NORMAL_AVG4, states "acc_perf_mode = 1 -> normal mode; acc_perf_mode = 0 -> average 4". So does that mean the example applied no averaging as it was in performance mode, but if I change to low power mode still with BMA4_ACCEL_NORMAL_AVG4 it will apply an average for each of x, y, and z based on 4 samples for each ? The same table on page 58 mentions OSR2 and OSR4 mode - what are they ?
Reply:acc_bwp had different meaning acooding acc_perf_mode value. If acc_perf_mode was set to 0, the sampling will be averaged. You could see it from data sheet.
Can you please help me to properly understand FIFO/watermark operation by responding to my middle paragraph in my previous post which is copy and pasted below ?
"I'm not properly understanding the watermark mode of operation, so can you help me to understand a little better, please ? I know the FIFO is 1024 bytes in total, and in this example watermark is set to 600 (which in headerless mode equates to 100 samples of x, y, and z because 600 / 6 = 100, and each sample group of x, y, and z is 3 x 2 bytes). Assuming the device begins filling its internal memory at "address 0" and continues until "address 1023" then is it true to say it will assert the mapped interrupt, in this case int1, when it reaches "address 599" ? Does it then continue filling memory upto "address 1023" but then assert int1 again (assuming it remains in the same mode) when it again reaches "address 599" ? Or does this all depend on the FIFO overflow setting ? So if I choose BMA4_FIFO_STOP_ON_FULL then will it stop sampling and filling the FIFO once it reaches "address 1023" ? And if this setting is not chosen will it continually sample and record going back to the start of FIFO after reaching the full mark ?"
Reply:When the FIFO length reaches 600 bytes, an interrupt will be triggered. At this time, the host needs to read the FIFO, otherwise the FIFO length will continue to increase. If the host reads 600 bytes of FIFO data, the FIFO length starts from 0 and then increases. If you choose BMA4_FIFO_STOP_ON_FULL. When FIFO was full, it willn't store latest new data to FIFO.
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Sorry. After confirmation, the software architecture of BSEC2 does not support 1 Hz sample rate, while BSEC1 supports 1 Hz sample rate. So you could see BSEC2 software, 1 Hz sample rate code was removed.
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Yes, the error is going to accumulate as time progresses.
It could be corrected periodically by referring to the local time. For example, after a few seconds, compare the local time with the accumulated time.
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