Take the INT1 pin as an input for example, below are the steps:
- Disable the INT1 output (by clearing Bit 3 in Register 0x53, which then will be 0).
- Set INT1 as an input, and select Level or Edge Sensitive (by writing 0x10 to Register 0x54).
- Connect the external input signal (Vsync) to the INT1 pin. Suppose that Vsync is an active high signal.
- In the FIFO, enable accel data, and enable FIFO header and FIFO TAG1 (0x58 in Register 0x47)
In normal stage, Vsync is low and the FIFO frame header is 0x84 (fh_ext<1:0> = 00). Once Vsync is issued, the related FIFO frame header will be 0x85 (fh_ext<1:0> = 01).
