your I2C seems to have a lot of error. The beginning caught my attention: Start, h50 [ h28 | WR ], h00, Restart, h51 [ h28 | RD ], hA0 NAK, Restart, h50 [ h28 | WR ], h3D, h00, Stop Error!!! There is a double i2c restart. I do not believe that the protocol allows for this. It should be one of these cases: 1: Start -> WADDR -> ACK -> REG -> ACK -> RESTART -> RADDR -> DATA [ -> ACK -> DATA ]*n -> NACK -> STOP 2: Start -> WADDR -> ACK -> REG -> ACK-> STOP -> START -> RADDR -> DATA [ -> ACK -> DATA ]*n -> NACK -> STOP 3: Start -> WADDR -> ACK -> REG -> ACK -> DATA [ -> ACK -> DATA ]*n -> ACK -> STOP Does you host configuration support clock streching ?
... View more