Hi Jacu, I haven't read the whole thread, but I see many snapshots from simulation data, and not a single one of the real bus. To be able to help you, please export the data from the bus, along with what it is supposed to be. We usually use Saleae Logic analyzers, they are excellent, but an oscilloscope output could also work. Simply compare the actual protocol on your bus with the Bosch protocol, (page 93 of the current datasheet) https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BNO055-DS000.pdf PS: I do see your last post about "spikes" during the ACK. This is normal, when the SDA transitions from being host-controlled to being slave-controlled, this happens. Only the status during rising edge of the SCL matters.
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