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    BMA400 Interrupt Status Register not reset

    BMA400 Interrupt Status Register not reset

    New Poster

    I program an application, where the BMA is in low power mode, till an threshold is reached. After that, the BMA should read acceleration values, as long, as the interrupt is . The interrupt is only triggered once, when passing the ., so i thought, i read the GEN1triggeredthreshold status-bit and as long at it is set, i read the acceleration data. But the bit is only set to 1 and not reset. Any suggestions ?
    Here my configuration:


    //Auto-lowpower relative
        setRawRegisterValue(AUTOLOWPOW_1_REG_ADDR, 0b00000010);      //Configure Auto low Power when still standing
        //Generic interrupt 1 (gen1) relative
        setRawRegisterValue(GEN1INT_CONFIG0_REG_ADDR, 0b11111000);   //Interrupt Condition: all axes, 100 Hz, auto update, hyst disable
        setRawRegisterValue(GEN1INT_CONFIG1_REG_ADDR, 0b00000001);   //Interrupt Condition: all axes must be under  the threshold
        setRawRegisterValue(GEN1INT_CONFIG2_REG_ADDR, 0b00000101);   //Interrupt Condition: Set treshold to 5*8mg/lsb = 40mg
        setRawRegisterValue(GEN1INT_CONFIG3_REG_ADDR, 0b00000000);   //Interrupt Condition: Monitor Duration Cofig3*256+gonfig31 = 100 Samples
        setRawRegisterValue(GEN1INT_CONFIG31_REG_ADDR, 0b01100100);   //Interrupt Condition: Monitor Duration 100 sample /100Hz = 1s
        //Auto-wakeup relative
        setRawRegisterValue(AUTOWAKEUP_1_REG_ADDR, 0b00000010);   //Configure Auto wakeup to switch from lowpower to normal mode
        //Wakeup interrupt relative
        setRawRegisterValue(WKUP_INT_CONFIG0_REG_ADDR, 0b11101110);   // Interrupt Condition: all Axis; 3/4 Samples; auto update
        setRawRegisterValue(WKUP_INT_CONFIG1_REG_ADDR, 0b00000011);   // Interrupt Condition: Wakeup threshold 94 mg @4g range
        setRawRegisterValue(AUTOLOWPOW_1_REG_ADDR, 0b00000010);      //Configure Auto wakeup to switch from lowpower to normal mode
        //HW Interrupt
        setRawRegisterValue(INT_CONFIG0_REG_ADDR, 0b00000100);   //Enable Gen1 Interrupt
        setRawRegisterValue(INT1_MAP_REG_ADDR, 0b00000100);   //Map Interrupts to Pin1 (Gen1 Interrupt)
        //setRawRegisterValue(INT1_MAP_REG_ADDR, 0b00000101);   //Map Interrupts to Pin (Gen1 + Wake Up Interrupt)
        setRawRegisterValue(INT2_MAP_REG_ADDR, 0b00000001);   //Map Interrupts to Pin2 (Wake Up Interrupt)
        setRawRegisterValue(INT12_IO_CTRL_REG_ADDR, 0b00100010);   //Configure Interrupt Behavior

    Here the function that checks the status register for bit 3 set:

    bool BMA400_Gen1_Intr_status(){
        int value =getRawRegisterValue(INT_STAT0_REG_ADDR, 1);
            return true;
            return false;


    3 REPLIES 3

    Community Moderator
    Community Moderator

    Hello Jones, 


    I'm little confused about your code because you are using your own definition. 

    But, generally you set wake-up threshold and always get INT_STATUS_0 value as 1. 

    I think because you enable x,y,z all axes and threshold is 90mg. 

    If BMA400 is on your board, X value should be 1g. Therefore, it is over 90mg. 

    That's why you already get wake-up interrupt, and never reset. 

    Simply, please test after disable x and only enable y,z. You could get the right result what you want 🙂 



    Oh then I'm confused.
    Because as you can see, I mappped the interrupts to the interrupt-pins. My microcontroller, only gehts triggerd when i shake the bma.
    Isn't the 90mg change ? So when there is 90mg change in 1 seconde for example ?

    Thanks allready for your help.

    Community Moderator
    Community Moderator

    Hello Jones, 


    I don't understand your reply fully. 

    I mean you enable x,y,z all axes and your threshold is 90mg. 

    Let's say if BMA400 is on your board. Z value should be around 1G right? ( Reversely -1 G) 

    Therefore, Z value is always over your threshold for your wake up threshold, so can't be reset. 

    To be specific, even though you reset mandatory, it will be set again right after.