Hi td-filip,
Thank for your inquiry.
Sorry for the delayed reply. The ODR of acc_filt2 is fixed at 100 Hz. When configured as acc_filt2, the bandwidth is ODR/2. When configured as acc_filt_1p, the bandwidth is 1Hz.
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Hi td-filip,
BMA400 activity change algorithm is implemented internally on the ASIC. The "curr_value" and "last_value" are hidden so that users are not able to read them through I2C/SPI interface.
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