BMI323 no interrupt when FIFO and TAP occurs at the same time

[Sunil_googly]

Hi

I am using BMI323 for getting accelerometer FIFO and tap events.
I configured BMI323 interrupts as edge-triggered and enabled
FIFO watermark and Tap interrupts.

I observed that when both interrupts coincide, the host
is not getting the interrupts, but in the INT1 or INT2 status register,
the corresponding event bit is high. If I manually read the status
register then interrupts start working.

When tested individually the tap or FIFO watermark interrupt works
properly.

How do I get both FIFO and tap interrupts at the same time?

I2C

00: 1143
01: 0000
02: 00e0
03: fe56
04: 00dd
05: 0fb8
06: ffff
07: fff5
08: 0000
09: 1539
0a: 5331
0b: 0023
0c: 0000
0d: 4100
0e: 0000
0f: 0000
10: 3000
11: 0001
12: 012c
13: 0000
14: 0002
15: 03f6
16: fe3a
17: 0000
18: 0000
19: 0000
1a: 0000
1b: 0000
1c: 0000
1d: 0000
1e: 0000
1f: 0000
20: 402a
21: 404a
22: 0000
23: 0000
24: 0000
25: 0000
26: 0000
27: 0000
28: 3206
29: 1206
2a: 0000
2b: 0000
2c: 0000
2d: 0000
2e: 0000
2f: 0000
30: 0000
31: 0000
32: 0000
33: 0000
34: 0000
35: 00b4
36: 0600
37: 0000
38: 0006
39: 0001
3a: 0000
3b: 1001
3c: 0000
3d: 0000
3e: 0000
3f: 0000
40: 0001
41: 001e
42: 0000
43: 0002
44: 0000
45: 0001
46: 0000
47: 0008
48: d6a1
49: 0012

spi
00: 1143
01: 0000
02: 00e0
03: 0084
04: 0097
05: 1013
06: fffd
07: fffe
08: 0001
09: 14f1
0a: de0f
0b: 001d
0c: 0000
0d: 0000
0e: 4100
0f: 0000
10: 3000
11: 0001
12: 012c
13: 0000
14: 0002
15: 03f6
16: 005f
17: 0000
18: 0000
19: 0000
1a: 0000
1b: 0000
1c: 0000
1d: 0000
1e: 0000
1f: 0000
20: 402a
21: 404a
22: 0000
23: 0000
24: 0000
25: 0000
26: 0000
27: 0000
28: 3206
29: 1206
2a: 0000
2b: 0000
2c: 0000
2d: 0000
2e: 0000
2f: 0000
30: 0000
31: 0000
32: 0000
33: 0000
34: 0000
35: 0078
36: 0600
37: 0000
38: 0500
39: 0000
3a: 0000
3b: 2002
3c: 0000
3d: 0000
3e: 0000
3f: 0000
40: 0001
41: 001e
42: 0000
43: 0002
44: 0000
45: 0001
46: 0000
47: 0008
48: d6a1
49: 0012

Thanks

[BSTRobin]

Hi Sunil_googly,

I upload exampel code on STM32 for your reference. Based on Github's BMI323 sensor API & example code(https://github.com/boschsensortec/BMI323-Sensor-API), you should define a global variable before you call bmi323_map_interrupt() fucntion to map interrupt TAP and FIFO watermark.

struct bmi3_map_int bmi323_map_int = { 0 };

int8_t Open_BMI323_TAP(struct bmi3_dev *dev)
{
...
bmi323_map_int.tap_out = BMI3_INT1;

/* Map the feature interrupt for tap interrupt. */
rslt = bmi323_map_interrupt(bmi323_map_int, dev);
...
}

int8_t Open_BMI323_FIFO(struct bmi3_dev *dev)
{
...
bmi323_map_int.tap_out = BMI3_INT1;

/* Map the interrupt configuration */
rslt = bmi323_map_interrupt(bmi323_map_int, dev);
...
}

[Sunil_googly]

Hi BSTRobin,

Thank you for your response.

I have configured both Tap and FIFO watermark interrupts, but the issue I'm facing is that I am not receiving interrupts when I tap the device while the FIFO watermark is active. I am checking the INT1 status register and reading the FIFO data in the interrupt handler.

I have configured the Accelerometer and Gyroscope Output Data Rate (ODR) to 400Hz, enabled the FIFO watermark at 5 frames, and also enabled Tap interrupts. Currently, I am receiving watermark interrupts every 5 frames. However, as soon as I tap the device, the FIFO watermark and Tap interrupts cease to occur.

When the device stops giving interrupts, the FIFO length reaches 0x3f6, and if I manually read the FIFO_DATA, then the interrupts restart. However, after some time, they get stuck again when I tap the device. Since there is no interrupt, I am unable to read FIFO data in IRQ handler. I observed this issue when BMI323 is interfaced with I2C and the interrupt is configured as an edge trigger.

Is there anything you can suggest to resolve this issue?

Thanks

[BSTRobin]

Hi Sunil_googly,

As you set 400 Hz ODR and FIFO watermark at 5 frames, FIFO watermark interrupt will occur every 12.5 ms, FIFO length should be 60 bytes(headless mode, 12*5 frames = 60 bytes).
When FIFO length reaches 0x3f6, it indicates that the interrupt handler on the host side did not respond in a timely manner, resulting in FIFO not being read in a timely manner and the interrupt being suspended.

As you have set a high ODR and a small FIFO watermark level, you need to ensure that the host can respond to interrupt programs in a timely manner.

[Sunil_googly]

Hi BSTRobin,

I tested by setting 400 Hz ODR and FIFO watermark at higher number for example 100 frames (Accelero and Gyro) samples which is of 600 words and 150 frames (Accelero and Gyro) samples which is of 900 words with Tap interrupt enabled but in these cases also as soon as I tap the device, the FIFO watermark and Tap interrupts stops.

If I reduce the ODR then I am able to get all the Fifo watermark and Tap interrupts.
If I test only FIFO watermark at 400hz or higher then there is no problem I am getting continous interrupts when FIFO hits watermark.
If I test only Tap then there is no problem continously I am getting interrupt when I tap the device.

The interrupt stops only when FIFO is running and if Tap interrupt occurs, I don't know whether it is due to BMI323 or host.
If host misses processing of watermark interrupt then FIFO reaches to FULL is there any way to configure FIFO overflow interrupt?

Thanks