Where can I get more details about register 0x5B and 0x5C? These two registers are not mentioned in datasheet. And why only 4 bit for register 0x5B(asic_lsb = ((index / 2) & 0x0F);) and shift 4 bit right to get msb for register 0x5C? I try to get the content of register 0x5b and 0x5c after config file is downaloaded and it showed 0x10(register 0x5C) and 0x00(register 0x5B). The setting of dev->read_write_len is 32 and the length of BMA4_CONFIG_STREAM_SIZE is 6144 bytes, the last write/index should be 6144-32=6112(0x17E0). So register 0x5C should be (6112/2 >>4)=0xBF and register0x5B= (6112/2)&0x0f=0x0? Obviously, the content of registetr 0x5B and ox5C are not what I expected.
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Am i correct for the following calculation? In order to suppress false triggers, the interrupt is only generated (cleared) if a certain number N of consecutive slope data points is larger (smaller) than the slope threshold given by (0x28) slope_th. This number is set by the (0x27) slope_dur bits. It is N = (0x27) slope_dur + 1 for (0x27). In EDT the duration of the wake-up phase depends on the number of samples required by the enabled interrupt engines. e.g. slope_dur=1, bandwidth=500Hz(tut=1ms), sleep time=6ms tactive = tut + tw,up1 - 0.9 ms (or tactive = tut + tw,up2 - 0.9 ms) N=slope_dur+1=2, so tactive=1ms*3+1.4ms(typical value)-0.9ms=3.5ms? and the estimated current will be (6ms*1.4uA+3.5ms*130uA)/(6ms+3.5ms)?
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