BMI323 no interrupt when FIFO and TAP occurs at the same time

[Sunil_googly]

Hi

I am using BMI323 for getting accelerometer FIFO and tap events.
I configured BMI323 interrupts as edge-triggered and enabled
FIFO watermark and Tap interrupts.

I observed that when both interrupts coincide, the host
is not getting the interrupts, but in the INT1 or INT2 status register,
the corresponding event bit is high. If I manually read the status
register then interrupts start working.

When tested individually the tap or FIFO watermark interrupt works
properly.

How do I get both FIFO and tap interrupts at the same time?

I2C

00: 1143
01: 0000
02: 00e0
03: fe56
04: 00dd
05: 0fb8
06: ffff
07: fff5
08: 0000
09: 1539
0a: 5331
0b: 0023
0c: 0000
0d: 4100
0e: 0000
0f: 0000
10: 3000
11: 0001
12: 012c
13: 0000
14: 0002
15: 03f6
16: fe3a
17: 0000
18: 0000
19: 0000
1a: 0000
1b: 0000
1c: 0000
1d: 0000
1e: 0000
1f: 0000
20: 402a
21: 404a
22: 0000
23: 0000
24: 0000
25: 0000
26: 0000
27: 0000
28: 3206
29: 1206
2a: 0000
2b: 0000
2c: 0000
2d: 0000
2e: 0000
2f: 0000
30: 0000
31: 0000
32: 0000
33: 0000
34: 0000
35: 00b4
36: 0600
37: 0000
38: 0006
39: 0001
3a: 0000
3b: 1001
3c: 0000
3d: 0000
3e: 0000
3f: 0000
40: 0001
41: 001e
42: 0000
43: 0002
44: 0000
45: 0001
46: 0000
47: 0008
48: d6a1
49: 0012

spi
00: 1143
01: 0000
02: 00e0
03: 0084
04: 0097
05: 1013
06: fffd
07: fffe
08: 0001
09: 14f1
0a: de0f
0b: 001d
0c: 0000
0d: 0000
0e: 4100
0f: 0000
10: 3000
11: 0001
12: 012c
13: 0000
14: 0002
15: 03f6
16: 005f
17: 0000
18: 0000
19: 0000
1a: 0000
1b: 0000
1c: 0000
1d: 0000
1e: 0000
1f: 0000
20: 402a
21: 404a
22: 0000
23: 0000
24: 0000
25: 0000
26: 0000
27: 0000
28: 3206
29: 1206
2a: 0000
2b: 0000
2c: 0000
2d: 0000
2e: 0000
2f: 0000
30: 0000
31: 0000
32: 0000
33: 0000
34: 0000
35: 0078
36: 0600
37: 0000
38: 0500
39: 0000
3a: 0000
3b: 2002
3c: 0000
3d: 0000
3e: 0000
3f: 0000
40: 0001
41: 001e
42: 0000
43: 0002
44: 0000
45: 0001
46: 0000
47: 0008
48: d6a1
49: 0012

Thanks

[BSTRobin]

Hi Sunil_googly,

You can use a logic analyzer to capture the I2C/SPI waveform and check if all FIFO data have been read out after FIFO watermark interrupt occurs, and whether the speed of reading FIFO data is too slow.

[Sunil_googly]

Hi BSTRobin,

I verified by setting ODR at 400hz and the FIFO watermark at different levels, such as 900, 600, 100 words, etc., and I am reading complete FIFO contents until the watermark level. There is no problem in testing only the FIFO watermark.

The problem occurs when I enable the Tap and the FIFO watermark interrupts. The interrupt stops only when FIFO is running and if Tap interrupt occurs
This issue can also be observed with any-motion and FIFO watermark interrupts. The interrupt stops when FIFO is running and if any-motion interrupt occurs.

Please can you share any code reference where the FIFO watermark and tap or motion interrupts are enabled at 400 hz ODR?

Thanks

[BSTRobin]

Hi Sunil_googly,

The previously uploaded attachment code, FIFO watermark and TAP work well. You can change the ODR to 400 Hz and ensure that FIFO data is read in a timely manner.